Etching systems typically have a physical mechanism, such as a clamp ring, a clamp ring with clamp fingers, and the like, to retain a wafer on a chuck during an etching step. An etching system (not fully illustrated in FIG. 1) includes a clamp ring 16 with prior art clamp fingers 18 that extend onto portions of a semiconductor device substrate 10 as shown in FIG. 1. As used in this specification, a semiconductor device substrate includes a monocrystalline semiconductor wafer, a semiconductor-on-insulator wafer, or any other substrate used to form a semiconductor device. The semiconductor device substrate 10 includes a plurality of stepping fields 12, where each stepping field 12 includes one or more semiconductor devices (not identified within FIG. 1). Each clamp finger 18 has a single top surface 20 that slopes down at an angle away from the top of the clamp ring 16 and toward the semiconductor device substrate 10 as shown in FIG. 2. The fingers also have sides 22 and a distal end 24.
When etching a layer of material, such as polysilicon, with the clamp ring 16 in place, a residual amount of the polysilicon remains on the semiconductor device substrate 10 in areas near the clamp fingers 18. The clamp fingers 18 cover a portion of the polysilicon layer during the etching step, such that the polysilicon beneath the clamp fingers is unetched. Referring to FIG. 3, a polysilicon member 30 has a covered region 32 corresponding to an area beneath a clamp finger during the etching step and halo regions 34 that are near the sides of region 32. Halo regions 34 are typically only a fraction of the covered region 32. Portions of an insulating layer 60 are exposed after the etching step.
During subsequent processing, these halo regions 34 cause processing problems. More particularly, in a logic process flow, the halo regions 34 can delaminate from the substrate 10 and cause particle problems that spread over the substrate surface. These particles can cause electrical shorts and other problems that make the devices defective.
One attempt to solve the problem is to increase the overetch time to etch away most or all the halo region. This process does not work well when the polysilicon layer lies on a gate dielectric layer because the gate dielectric layer is relatively thin. During the overetch, pin holes are formed in the gate dielectric. After the pin holes are formed, the etching species used to etch the polysilicon layer attacks the semiconductor device substrate underlying the pin holes and forms pits within the substrate. Adding overetch time also increases cycle time which is undesired.
A need exists to form a semiconductor device on a semiconductor device substrate where delamination of polysilicon or other conductive materials will not occur and cause problems. A need further exists for finding a solution to the problem without having to add processing steps or use unusual or exotic materials.